1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for forming a suicide layer on a gate of a memory transistor in a dynamic random access memory (DRAM) device, and a gate and an interchangeable source/drain region of a periphery transistor in a periphery circuit of the DRAM device.
2. Description of Related Art
A DRAM is a kind of volatile memory. The DRAM includes a large number of memory cells and a periphery circuit, in which each memory cell includes a single transistor, such as a metal-oxide semiconductor (MOS) transistor with a capacitor, and can be randomly accessed. Each gate of the MOS transistors is electrically coupled to a word line, and one interchangeable source/drain region is electrically coupled to a bit line. The DRAM also includes an address decoder and a periphery circuit for an operation of the memory cells.
FIGS. 1A-1C are cross-sectional views of a DRAM device, schematically illustrating a conventional fabrication method for forming a silicide layer in the DRAM device. In FIG. 1A, a field oxide (FOX) layer 10 is formed on a semiconductor substrate 100 by thermal oxidation. The substrate 100 is also divided into two regions: a memory region 150 and a periphery region 160. A gate oxide layer 12 is formed over the substrate 100 by thermal oxidation. A polysilicon layer 14 is formed on the gate oxide layer 12. Patterning the polysilicon layer 14 and the gate oxide layer 12 forms a gate 50 at the memory region 150 and a gate 52 at the periphery region 160. Using the gates 50, 52 and the FOX layer 10 as a mask, a lightly doped region 16 is formed in the substrate 100. The lightly doped region 16 is a pre-processed region in order to form an interchangeable source/drain region with a lightly doped drain (LDD) structure on each side of the gates 50, 52.
In FIG. 1B, an insulating layer 18 is formed over the substrate 100. An etching back process is performed to etch the insulating layer 18 at the periphery region 160 so that the portion of the insulating layer 18 at the periphery region 160 is removed but leaves a residue, which forms a spacer 20 on each side of the gate 52. Here, a photoresist layer (not shown) has been involved serving as an etching mask. A doping process is performed to form a heavily doped region 22, in which the spacer 20 and the insulation layer 18 serve as a doping mask. The interchangeable source/drain region including the lightly doped region 16 and the heavily doped region 22 forms the LDD structure in the substrate 100 on each side of the gate 52. A MOS transistor including the gate 52 and the interchangeable source/drain region is formed at the periphery region 160.
In FIG. 1C, a silicide process is performed to form a silicide layer 24 on the polysilicon layer 14 of the gate 52 and on the heavily doped region 22. An etching back process is performed to remover the insulating layer at the memory region 150. A residue of the insulating layer 18 forms a spacer 26 on each side of the gate 50 at the memory region 150.
The rest fabrication processes to accomplish a DRAM device are well known by the one skilled the art, and are not further described here.
In this convention fabrication method, the silicide process is only performed at the periphery region 160. The reason is following. Even though the silicide layer 24 can increase the conductivity on the gate 52 and the interchangeable source/drain region of the MOS transistor at the periphery region 160, the silicide layer 24 also consumes the junction depth of the interchangeable source/drain. This may more severely cause a charge leakage to the substrate as the device dimension is more greatly reduced. Since each the memory cell in the DRAM uses a capacitor for storing information, if charges stored in the capacitor are leaking to the substrate, it gets more difficult to recharge the capacitor. This causes an access speed is reduced or even causes an error of information stored in the capacitor. That is why the silicide process is not performed on the MOS transistor 50 at the memory region 150.
Since the each memory cell is desired to have a fast access speed, if there is no silicide included, the access speed on the each memory cell cannot be increased. This is the main drawback of the conventional method for fabricating a DRAM device.